Performance and Area Scalable Cell Architecture Technology

ABSTRACT

An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to, the benefit of the filing date of,and hereby incorporates herein by reference, U.S. Provisional PatentApplication 60/746,579, entitled “Performance & Area Scalable CellArchitecture Technology,” and filed May 5, 2006.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not Applicable.

BACKGROUND OF THE INVENTION

The present embodiments relate to forming integrated circuits and aremore particularly directed to a performance and area scalable cellarchitecture technology.

The history and prevalence of integrated circuits are well known andhave drastically impacted numerous electronic devices. As a result andfor the foreseeable future, successful designers constantly areimproving integrated circuit design, and improvements are in numerousareas including device performance and size. In general, integratedcircuit design may be viewed in two steps, the first being electricalfunction and the second being physical layout. The latter attribute isthe focus of the preferred embodiments and, thus, is further introducedbelow.

As further detailed later in this document, the physical layout of anintegrated circuit is typically designed from layouts of smaller blocks.The smaller blocks are sometimes referred to as cells (or standardcells), and in this regard often designers establish different cellswhere each such cell has an associated functionality and layout. Forexample, the functionality may be to perform a logical function, such aninverter or other Boolean operation, including AND, NAND, OR, NOR, XOR,and XNOR, or the functionality may provide a storage function. Moreover,in some cases different cell layouts exist for the same functionality,where often the choice among those cells may be based on other eitherlocal or global circuit considerations, such as performance, speed, andpower consumption. Thus, to design a portion of an integrated circuit orthe entire circuit, an area is defined that will be physically locatedon the circuit, and cells for that area are chosen from a collection ofdifferent cells, typically referred to as a cell library (or plural,libraries). Each cell is selected from the library and located indifferent sub-areas within that area. In contemporary applications,these selections are performed by one or more processors operating inresponse to specialized software and data. In this regard, the softwareplaces the cells in locations along rows, where therefore the area orentire integrated circuit layout ultimately will include a very largenumber of such rows with cells aligned along each such row. Typicallyafter the location of each cell is established, then routing isaccomplished wherein interconnections are defined so as to connectvarious nodes of cell devices together.

In the context of cell libraries, the prior art includes variousdifferent cells. Among these cells are two different cells, shown inFIGS. 1 and 2, respectively, for implementing a pair of complementaryMOS transistors, that is, where one transistor is NMOS (i.e., ann-channel MOSFET) and the other transistor is PMOS (i.e., a p-channelMOSFET). Each of these cells is described below.

Looking to FIG. 1, it illustrates a plan view of a prior art transistorcell TC₁, having an NMOS transistor N₁ and a PMOS transistor P₁. Thesetwo transistors form a cell that is referred to as a single row cellbecause the cell has a boundary B₁ that spans across one row whenboundary B₁ is aligned between two successive row boundary lines RB₁ andRB₂, where row boundary lines RB₁ and RB₂ are imaginary lines used foralignment of cell TC₁ relative to other cells (not shown) in a physicalcircuit layout. NMOS transistor N₁ includes a first and second N-typesource/drain region S/D_(N1a) and S/D_(N1b) that are typically co-planarand diffused within a semiconductor substrate or region that is notperceptible from the perspective of FIG. 1, where the descriptor“source/drain” is used in this document to describe generically a regionthat may function either as a transistor source or a transistor drain,depending on connectivity to the transistor and so that when no suchconnectivity is illustrated, such a region could be either a source or adrain and, hence, is referred to as a source/drain. Further, NMOStransistor N₁ includes a gate region G_(N1) formed above and betweensource/drain regions S/D_(N1a) and S/D_(N1b) that (although thesource/drain regions may, in some approaches, extend to some extentunder the gate region, with various descriptions for such an approachsuch as extended drain or low doped drain). PMOS transistor P₁ includesa first and second P-type source/drain region S/D_(P1a) and S/D_(P1b)that are formed within an N-type well NW₁ (or N-well), where N-well NW₁is also formed in the above-mentioned semiconductor substrate or regionthat is not perceptible from the perspective of FIG. 1. PMOS transistorP₁ also includes a gate region G_(P1) formed above and betweensource/drain regions S/D_(P1a) and S/D_(P1b) (although the source/drainregions may, in some approaches, also extend to some extent under thegate region).

Looking to FIG. 2, it illustrates a plan view of a prior art transistorcell TC₂, having an NMOS transistor that is created in two different andnon-continuous areas, which for sake of this document and reference maybe referred to as half transistors in that ultimately they are connectedby interconnect (not shown) so that the respective gate and source/drainregions from each half transistor are electrically connected to oneanother to provide a single operational NMOS transistor. For sake ofreference, therefore, one NMOS half transistor N_(2.1) is shown at thebottom of cell TC₂ and another NMOS half transistor N_(2.2) is shown atthe top of cell TC₂. Moreover, cell TC₂ also includes a PMOS transistorP₂. Thus, for cell TC₂, PMOS transistor P₂ and the entirety of the NMOStransistor that is formed by half transistors N_(2.1) and N_(2.2) form acell that is referred to as a double row cell because the cell has aboundary B₂ that aligns on its ends along boundary row lines and spansacross two adjacent rows, as defined between a row boundary line RB₁,across a next successive row boundary line RB₂, and then reachinganother row boundary line RB₃, where again the row lines are imaginarylines used for alignment of cell TC₂ relative to other cells (not shown)along the same rows in a physical circuit layout. NMOS half transistorN_(2.1) includes a first and second N-type source/drain regionS/D_(N2.1a) and S/D_(N2.1b) that are typically co-planar and diffusedwithin a semiconductor substrate or region that is not perceptible fromthe perspective of FIG. 2, and a gate region G_(N2.1) is formed aboveand between source/drain regions S/D_(N2.1a) and S/D_(N2.1b) (whereagain the source/drain regions may, in some approaches, extend to someextent under the gate region). Similarly, NMOS half transistor N_(2.2)includes, physically removed from NMOS half transistor N_(2.1), a firstand second N-type source/drain region S/D_(N2.2a) and S/D_(N2.2b) thatare typically co-planar and diffused within the above-mentionedsemiconductor substrate or region, and a gate region G_(N2.2) is formedabove and between source/drain regions S/D_(N2.2a) and S/D_(N2.2b).Note, therefore, that the overall source or drain regions of NMOStransistor N2 are in effect interrupted, that is, along their width(i.e., parallel to the length of their respective gate regions G_(N2.1)or G_(N2.2)) they do not provide a continuous diffused source orcontinuous diffused drain region as is implemented for NMOS transistorN₁ in transistor cell TC₁, but instead the diffused or planar width ofthe source or drain is separated into two different regions; in otherwords, assume for sake of reference that source/drain region S/D_(N2.1a)is connected as a source in a given architecture, and likewisesource/drain region S/D_(N2.2a) is connected as a source in the givenarchitecture; thus, the entirety of the combined widths of these twoco-planar sources operate as a source for an NMOS transistor, but thosetwo co-planar source regions are not continuous but instead separatedphysically from one another in the substrate (or well) into which theyare formed. As a result, there is a loss of performance. Continuing withtransistor cell TC₂, PMOS transistor P₂ includes a first and secondP-type source/drain region S/D_(P2a) and S/D_(P2b) that are formedwithin an N-well NW₂, where N-well NW₂ is also formed in theabove-mentioned semiconductor substrate or region. PMOS transistor P₂also includes a gate region G_(P2) formed above and between source/drainregion S/D_(P2a) and S/D_(P2b).

Transistor cells TC₁ and TC₂ provide advantageous operation in variouscircuit applications. The art recognizes, however, that the choicebetween these cells involves tradeoffs. Specifically, transistor cellTC₁ is smaller and therefore consumes less area on the integratedcircuit die as compared to transistor cell TC₂, where lower space usageis often important. Conversely, transistor cell TC₂ operates faster thattransistor cell TC₁, and this faster speed is often desirable.Accordingly, this tradeoff also must be considered in circuit design andthe prior art thereby provides drawbacks in its limitations of availablecells with these tradeoffs. Against this background, the preferredembodiments include an additional cell layout that may be combined withthe preceding cells and still others to provide further alternatives andadditional performance benefits in some applications, as is appreciatedfrom the remainder of this document.

BRIEF SUMMARY OF THE INVENTION

In one preferred embodiment there is an integrated circuit. Theintegrated circuit comprises an area having a layout aligned in rows.Each row is definable by a pair of row boundaries. The integratedcircuit also comprises a plurality of cells, comprising a first set ofcells. Each cell in the first set of cells spans at least two rows andcomprises a PMOS transistor having a source/drain region that spansacross one of the row boundaries and an NMOS transistor having asource/drain region that spans across one of the row boundaries.

Other aspects are also disclosed and claimed.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 illustrates a plan view of a prior art single row transistorcell.

FIG. 2 illustrates a plan view of a prior art double row transistorcell.

FIG. 3 illustrates a block diagram of a system for developing circuitdesign layer data in response to, among other things, a circuit celllibrary.

FIG. 4 illustrates a plan view of transistor cell per a preferredembodiment.

FIG. 5 illustrates a simplified layout diagram of all three cellsdescribed above, namely, transistor cells TC₁, TC₂, and TC₃.

FIG. 6 illustrates a layout LYT that includes all of the threetransistor cells TC₁, TC₂, and TC₃ and with power conductors spanningacross all those cells in a same dimension.

FIG. 7 illustrates another layout diagram of the three cells TC₁, TC₂,and TC₃ as well as a modified cell TC₃ as an alternative embodiment.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 and 2 were described above in the Background Of The Inventionsection of this document and the reader is assumed familiar with thatdiscussion.

FIG. 3 illustrates a block diagram of a system 10 for forming circuitdesign layer (“CDL”) data 12, where CDL data 12 presents the layout forcircuit elements in an area, such as for a very large number of suchelements in very large scale integration (“VLSI”) or otherarchitectures. CDL data 12 is later used to generate an integratedcircuit 13, where more typically CDL data 12 is used with additionalrules and data to form a reticle, multiple reticles, or the like, andthat reticle is thereafter used with photolithography processes tocreate a corresponding integrated circuit. These latter steps are knownin the art and therefore not detailed herein but rather the focus is onvarious inventive aspects.

Turning now to FIG. 3 in more detail, and by way of introduction, thegeneral nature of system 10 is known in the art, but novel aspects areadded thereto and improve CDL data 12, and the integrated circuit to beformed in response to that data, for reasons appreciated throughout theremainder of this document. System 10 in general includes a processorsystem 14 that may be embodied in various different forms of hardwareand software, typically including one or more processors and/orcomputing devices. Processor system 14 has one or more interfaces 16coupled to a data input store 18, where data input store 18 representsany of various forms of storage such as drives and memory, and wheresuch storage may retain program or other data that may be read/writtenwith respect to processor system 14. Data store 18 is shown to providefour input data files 18 ₁ through 18 ₄ via interface 16 to processorsystem 14, and each of these files is discussed below. Further, inresponse to these four input data files, processor system 14 provides,as an output, CDL data 12, which may be used as described above. Lastly,note that system 10 may include numerous other aspects such as arecommon with various computing configurations, including other inputdevices (e.g., keyboards, mouse, touch pad, tablet, and the like),output devices (e.g., display, monitor, and the like), as well as othermedia, components, devices, and peripherals, although such aspects areneither shown nor described so as to simplify the present discussion.

Input data file 18 ₁ from data store 18 to processor system 14 isdesignated netlist 18 ₁. Netlist 18 ₁ represents a description ofdevices as defined by their nodes and the functionality of each deviceas between their nodes, where such devices may include any circuitelement including transistors, resistors, capacitors, and so forth.Further, netlist 18 ₁ includes the connections between these devices aswell as their terminals, or “ports,” to the external environment.

Input data file 18 ₂ from data store 18 to processor system 14 isdesignated cell library 18 ₂. As introduced earlier, a cell library, andtherefore cell library 182, is a collection of descriptors of thephysical layouts of the component or multiple components that form arespective electrical device or devices, where each layout is referredto as a cell or standard cell. Thus, for each component, such as onemore individual circuit elements, logical functions, or storageelements, one or more cells are included in cell library 182 todesignate a corresponding one or more physical layout of the layers usedin integrated circuit construction to implement the component. Again,the inclusion of more than one cell for a given component is providedbecause in some instances the selection of one cell for that componentis a better choice as opposed to a different cell for that samecomponent, such as in the choice between the transistor cells TC₁ andTC₂ shown in FIGS. 1 and 2, as described earlier.

Input data file 18 ₃ from data store 18 to processor system 14 is anElectronic Design Automation (“EDA”) computer program 18 ₃, whichtypically when executed by a processor performs various operations withrespect to data such as data files 18 ₁ and 18 ₂. Specifically, the EDAoperations typically include so-called placement and routing andtherefore program 18 ₃ is sometimes referred to as a P&R program ortool. Placement in the EDA context refers to the assignment of alocation for each component in netlist 18 ₁, as guided by certain rulesthat accompany the placement determination. In other words, EDA program18 ₃, when executed by processing system 14, defines a two-dimensionalarea that corresponds to the area of integrated circuit 13 to beconstructed, and the placement operation of EDA computer program 18 ₂then determines the location within that area for each component innetlist 18 ₁ so that the determined placement is according to, and doesnot violate, the accompanying placement rules. FIGS. 1 and 2, introducedearlier, depict examples of the placement of cells TC₁ and TC₂,respectively, where such placement is typically by alignment of the aboundary border in at least one dimension such as along rows that by wayof example in FIGS. 1 and 2 are shown between either row boundary linesRB₁ and RB₂ or row boundary lines RB₁ and RB₃. After placement, routingin the EDA context refers to the determination of where interconnectsare to be located in each cell and between such cells. The interconnectsare conductors of both signals between devices as well as power supplylines (high and low, including ground). As also demonstrated later, andin connection with routing, each cell has a number of so-called tracksassociated with it, where each track represents a different parallelimaginary line, parallel to the row, and crossing the cell at adifferent height dimension. Given the tracks, they provide locationindications or guides along which an interconnect may be placed. Forexample, transistor cell TC₁ of FIG. 1 is sometimes referred to as an8-track cell in that it has 8 such imaginary lines (not shown) extendingparallel to and in between row boundary lines RB₁ and RB₂. Similarlytransistor cell TC₂ of FIG. 2 is sometimes referred to as a 16-trackcell in that it has 16 such imaginary lines (not shown) extendingparallel to and in between row boundary lines RB₁ and RB₂. Because eachtrack across a cell represents a passageway at a different height, thenif an interconnect extends along one such track it will not physicallycontact or interfere with a different interconnect along a differenttrack across the same cell. The interconnects also include conductorportions that may extend from a track toward components in the cell,where such conductors are sometimes referred to as vias or plugs.Further, in the prior art often the power supply lines (e.g., V_(DD),V_(SS)) are dedicated to the same tracks across a large number of cellsso that the power lines may be efficiently routed to provide power tothe components in each such cell. Lastly, note that EDA is sometimesassumed to include the operation of synthesis so as to create netlist 18₁, such as from a register transfer level (“RTL”) description, but forsake of simplifying the present discussion netlist 18 ₁ is simply shownin FIG. 2 as a separate data input file to processor system 14.

Input data file 18 ₄ from data store 18 to processor system 14 is designrules file 18 ₄, which verifies or constrains the routing and placing ofEDA computer program 18 ₃. Specifically, the design rules of file 18 ₄are checked to ensure that there are no violations of certainparameters, typically specified by the manufacturer, sometimes referredto as the “foundry,” that will build integrated circuit 13. For example,such rules may pertain to transistor feature spacing, metal layerthickness, and power density rules.

The operation of system 10 is well known in the art and also should beunderstood with reference to the descriptions above of the various inputfiles, where system 10 is further improved in the preferred embodimentsby the addition of a novel cell into library 18 ₂, thereby improving theoverall system 10, its output CDL data 12, and any integrated circuit 13manufactured from such data. Briefly discussing such operation,processor system 14 inputs netlist 18 ₁ and per EDA file 18 ₃ selectsthe appropriate cells from cell library 18 ₂ and places and routes themin a two dimensional space. Further, the placement and routing is perdesign rules 18 ₄, where any violations of such rules are flagged and orcorrected. Once the violations are corrected or accepted, the resultfrom processor system 14 is in the form of CDL data 12. Further in thisregard, therefore, CDL data 12 thus provides a digitization of multipledesired circuit layers, thereby illustrating respective desiredcorresponding images to be formed on respective reticles so that eachcircuit layer may be formed later on a wafer and with features in thesame shape and with scaled dimensions of the image, and that wafer isseparated into pieces where many or all of those piece each providesintegrated circuit 13. Accordingly, CDL data 12 may indicate locations,layout, shape, and dimensions of features to be formed on a wafer andultimately in integrated circuit 13. One skilled in the art willappreciate numerous other examples of types of structures and layersthat may be indicated in CDL data 12.

FIG. 4 illustrates a plan view of transistor cell TC₃ per a preferredembodiment and for inclusion, by way of example, into cell library 18 ₂so as to improve CDL data 12 and integrated circuit 13 that isultimately is constructed from that data. By way of introduction,transistor cell TC₃ has a border B₃ that is again aligned along rowboundaries but that spans three rows. Particularly, in this preferredembodiment, and as detailed later, transistor cell TC₃ is positioned andaligned so that it spans across three cell rows, occurring between rowboundary lines RB₁ and RB₄. More particularly and in one embodiment,transistor cell TC₃ includes a first spare area SA₁ in part of the areabetween row boundary lines RB₁ and RB₂, a second spare area SA₂ in partof the area between row boundary lines RB₃ and RB₄, an NMOS transistorN₃ and PMOS transistor P₃. Each spare area SA_(r) is referred to as“spare” in the sense that it does not include any of the componentsneeded to implement either of the cell's transistors, but those samespare areas SA_(x) may instead be occupied by other components inaddition to the transistors that are in transistor cell TC₃. Withrespect to the transistors of transistor cell TC₃, they are describedimmediately below.

Looking now to NMOS transistor N₃ and PMOS transistor P₃, in theembodiment in FIG. 4, these two transistors along with spare areas SA₁and SA₂ form a cell that may be referred to as a triple row cell becausethe boundary B₃ around those devices extends along three rows as betweenrow boundary lines RB₁ and RB₄. As with the prior art, boundary line B₃is an imaginary border, here with respect to cell TC₃, and is used foraligning the cell relative to other cells (not shown) in a physicalcircuit layout. NMOS transistor N₃ includes a first and second N-typesource/drain region S/D_(N3a) and S/D_(N3b) that are formed within asemiconductor substrate or region that is not perceptible from theperspective of FIG. 4. NMOS transistor N₃ also includes a gate regionG_(N3) formed above and between source/drain regions S/D_(N3a) andS/D_(N3b) (although the source/drain regions may, in some approaches,extend to some extent under the gate region). PMOS transistor P₃includes a first and second P-type source/drain region S/D_(P3a) andS/D_(P3b), each of which is formed within an N-type well NW₃ (orN-well), where N-well NW₃ is also formed in the above-mentionedsemiconductor substrate or region that is not perceptible from theperspective of FIG. 4. PMOS transistor P₃ also includes a gate region G₃formed above and between source/drain regions S/D_(P3a) and S/D_(P3b)(although the source/drain regions may, in some approaches, extend tosome extent under the gate region).

Attention is now directed to the a real differences as between thetransistor cell TC₃, as compared to transistor cells TC₁ and TC₂ of theprior art. As introduced above, in one embodiment transistor cell TC₃spans three rows, whereas transistor cell TC₁ spans only a single rowand transistor TC₂ spans two rows. This difference in a preferredembodiment is now explored in greater detail, starting first withreference to FIG. 5. FIG. 5 illustrates a simplified layout diagram ofall three cells described above, namely, transistor cells TC₁, TC₂, andTC₃. To simplify the FIG. 5 illustration, each cell TC_(x) is shown byits respective boundary B₁, B₂, and B₃. With this illustration, oneskilled in the art may easily appreciate the difference in area occupiedby each cell. From FIG. 5, therefore, note that transistor cell TC₃consumes more area than either transistor cell TC₁ or transistor cellTC₂. However, recall that the area of transistor cell TC₃ includes spareareas SA₁ and SA₂. Therefore, various different versions of the cell maybe further specified to include additional items in the area. Forexample, within each spare area there may be provided transistorssmaller than NMOS transistor N₃ and PMOS transistor P₃ (e.g., for use ina flip-flop or multiplexer), decoupling capacitors or transistors,diffusion antenna protection devices, and failure analysis targets.

In addition to the preceding, and returning now to FIG. 4, transistorcells TC₃ may be appreciated to provide various benefits over the priorart, and these benefits in various instances may render the selection oftransistor cells TC₃ favorable over the prior art transistor cells TC₁and TC₂. Specifically, in a comparison of transistor cell TC₃ totransistor cell TC₁, the width of each source or drain region (shown inthe vertical dimension and parallel to the respective gate) is greaterfor transistor cell TC₃. As a result, the switching delay for transistorcell TC₃ is lower than that of transistor cell TC₁, that is, transistorcell TC₃ provides better speed performance. In a comparison oftransistor cell TC₃ to transistor cell TC₂, note that transistor cellTC₂ has various limitations that do not exist in transistor cell TC₃.For example, transistor cell TC₂ has an efficiency loss in that its halftransistors in effect provide two physically separated or non-continuoussource regions and two physically separated or non-continuous drainregions; these regions require interconnects to connect the respectivesource and drain regions of NMOS half transistor N_(2.1) and NMOS halftransistor N_(2.2). Further, layout rule checks require certain minimumspace requirements, such as between N-well NW₂ of PMOS transistor P₂ andboth the source/drain regions S/D_(N2.1a) and S/D_(N2.1b) of NMOS halftransistor N_(2.1) and the source/drain regions S/D_(N2.2a) andS/D_(N2.2b) of NMOS half transistor N_(2.2), and also as between gateconductor GP₂ and both gate conductors GN_(2.1) and GN_(2.2); as aresult, a certain amount of transistor width is lost for NMOS transistorN₁. Thus, there is a loss of transistor width in transistor cell TC₂,and there is greater transistor level intraparasitic effect, as comparedto transistors P₃ and N₃ of transistor cell TC₃. Particularly,transistor cell TC₃ includes a single PMOS transistor P₃ and a singleNMOS transistor N₃, without having to divide (e.g., halve) either suchtransistor into portions, so both of these latter transistors benefit.Further, in transistor cell TC₃, there is therefore less unusedtransistor area in one cell. In addition, note that by having transistorcell TC₃ span three rows in one embodiment, it is compatible withcontemporary placement and routing tools and therefore may be readilyincluded in cell library 18 ₂ and processed per EDA program 18 ₃ withoutany changes to the latter. Thus, using system 10, transistor cell TC₃may be mixed with other transistor cells (e.g., TC₁ and TC₂) in a givenlayout for integrated circuit 13.

For sake of further appreciating the inventiveness of the preferredembodiments, FIG. 6 illustrates a layout LYT that includes all of thethree transistor cells TC₁, TC₂, and TC₃ described earlier in thisdocument, with an example of various interconnects and to appreciate howsuch cells may be presented in CDL data 12 and likewise formed onintegrated circuit 13. Further, certain reference numbers from earlierFigures are carried forward into FIG. 6 while others are changed tosimplify the illustration and the discussion of additional connectionsillustrated therein. Additionally, and as discussed earlier, system 10aligns cells in an area along rows, and in this regard in FIG. 6 threesuch rows are shown, namely, a ROW₁ between row boundary lines RB₁ andRB₂, a ROW₂ between row boundary lines RB₂ and RB₃, and a ROW₃ betweenrow boundary lines RB₃ and RB₄. As discussed earlier, each cell, andhence each ROW_(x) in FIG. 6, has a number of tracks associated with it,where in FIG. 6 such tracks are shown only in ROW₁ so as not tooverburden the Figure, and are designated TRK₁ through TRK₈; each trackTRK_(r) represents a different imaginary line parallel to the rowboundary and crossing the cell/row at a different height dimension, andalong which an interconnect may be placed. Thus, since transistor cellTC₁ spans only one row (e.g., ROW₁), then it is considered an 8-trackcell; however, since the larger transistor components of transistor cellspans two rows, then that cell may be considered 16-track cells. Also inthis regard, in layout LYT power conductors are shown along certaintracks, where recall that system 10 determine the location and route ofsuch conductors as part of the routing operation from EDA computerprogram 18 ₂. Thus, in ROW₁, a V_(SS) power conductor is shown alongtrack TRK₁, and a V_(DD) power conductor is shown along track TRK₈.Similarly in ROW₂ and ROW₃, one skilled in the art will appreciated thatthere is a V_(SS) and V_(DD) power conductor at the tracks nearest therow line boundaries for each such row, where in ROW₂ the V_(SS) powerconductor is at the bottom track (i.e., nearest boundary line RB₂) andthe V_(DD) power conductor is at the top track (i.e., nearest boundaryline RB₃), where in opposite fashion in ROW₃ the V_(SS) power conductoris at the top track (i.e., nearest boundary line RB₄) and the V_(DD)power conductor is at the bottom track (i.e., nearest boundary lineRB₃).

Continuing with layout LYT, each transistor cell TC_(x) includesadditional interconnects so that the transistors in each cell form arespective inverter, which as well known in the art comprises ap-channel transistor having it source connected to V_(DD), an n-channeltransistor having its source connected to V_(SS), the gates of the twotransistors connected to one other and acting as an input, and thedrains of the two transistors connected to one other and acting as anoutput.

Looking at the connections forming an inverter in transistor cell TC₁, asingle gate G₁ is shown connecting the gate regions of PMOS transistorP₁ and NMOS transistor N₁, and gate G₁ is further connected to anoverlying gate conductor GC₁. Further, a drain conductor DC₁ connectsthe respective drains DP₁ and DN₁ of PMOS transistor P₁ and NMOStransistor N₁. Lastly, the source SP₁ of PMOS transistor P₁ is connectedby a plug PG_(DD) to the V_(DD) conductor along the top track of ROW₂,and the source SN₁ of NMOS transistor N₁ is connected by a plug PG_(SS)to the V_(SS) conductor along the bottom track of ROW₂.

Looking at the connections forming an inverter in transistor cell TC₂, asingle gate G₂ is shown connecting the gate regions of PMOS transistorP₁ and NMOS half transistors N_(2.1) and N_(2.2), and gate G₂ is furtherconnected to an overlying gate conductor GC₂. Further, a drain conductorDC₂ connects the drain DP₂ of PMOS transistor P₂ with the drain DN_(2.1)of NMOS half transistor N_(2.1) and with the drain DN₂.₂ of NMOS halftransistor N_(2.2). The source SP₂ of PMOS transistor P₂ is connected byrespective plugs PG_(DD) to the V_(DD) conductor along the top track ofROW₂ and to the V_(DD) conductor along the bottom track of ROW₃. Lastly,the source SN_(2.1) of NMOS half transistor N_(2.1) is connected by aplug PG_(SS) to the V_(SS) conductor along the bottom track of ROW₂, andthe source SN_(2.2) of NMOS half transistor N_(2.2) is connected by aplug PG_(SS) to the V_(SS) conductor along the top track of ROW₃.

Looking at the connections forming an inverter in transistor cell TC₃, asingle gate G₃ is shown connecting the gate regions of PMOS transistorP₃ and NMOS transistor N₃, and gate G₃ is further connected to anoverlying gate conductor GC₃. Further, a drain conductor DC₃ connectsthe drain DP₃ of PMOS transistor P₃ with the drain DN₃ of NMOStransistor N₃. The source SP₃ of PMOS transistor P₃ is connected byrespective plugs PG_(DD) to the V_(DD) conductor along the bottom trackof ROW₃ and to the V_(DD) conductor along the top track of ROW₂. Lastly,the source SN₃ of NMOS transistor N₃ is connected by respective plugsPG_(SS) to the V_(SS) conductor along the bottom track of ROW₂ and tothe V_(SS) conductor along the top track of ROW₁.

Given layout LYT, one skilled in the art may further appreciate theabove-noted differences between the inventive transistor cell TC₃ andtransistor cells TC₁ and TC₂. Moreover, layout LYT also depicts thebenefits of transistor cell TC₃ as mentioned above, including theavailability of spare areas SA₁ and SA₂ for use with other devices andthe ability to align transistor cell TC₃ along three rows, therebyrendering it compatible with contemporary placement and routing tools.In addition, layout LYT demonstrates that transistor cell TC₃ has anorientation whereby the source/drain region of both its PMOS transistorand its NMOS transistor spans across a respective row boundary and, as aresult, it accommodates the power conductors and metal pitch of otherstandard cells, where for example in FIG. 6 it may be seen that powerconductors V_(SS) and V_(DD) pass along the same track for eachdifferent cell. Note therefore, that transistor cell TC₃ may be combinedwith other standard cells, such as cells TC₁ and TC₂ within a so-callsoft region or block of an area on an integrated circuit. Accordingly,very high performance circuit can be formed from transistor cells of thetype of transistor cell TC₃ while lower performance requiring areas(e.g., control logic) may be constructed using 8-track cells such astransistor cell TC₁. Still other observations and benefits will beappreciable by one skilled in the art.

FIG. 7 illustrates another layout diagram of all three cells describedabove, namely, transistor cells TC₁, TC₂, and TC₃. For sake ofconvention, each transistor cell of the type of transistor cell TC₁includes an identifier TC_(1.x), where the different number of x depictsdifferent instances of a single row transistor cell of the type inFIG. 1. Similarly, each transistor cell of the type of transistor cellTC₂ includes an identifier TC_(2.x), where the different number of xdepicts different instances of a double row transistor cell of the typein FIG. 2. Still further, each transistor cell of the type of transistorcell TC₃ includes an identifier TC_(3.x), where the different number ofx depicts different instances of a triple row transistor cell of thetype in FIG. 4; indeed, for each such instance, note further that eachcell TC_(3.x) includes a spare area SA_(3.x.2) at its top and a sparearea SA_(3.x.1) at its bottom, as described earlier in connection withFIG. 4. Moreover, as to these cells TC_(3.x), each occupies three rowsas described earlier. For example, transistor cell TC_(3.1), is locatedin the row between row boundary lines RB₁ and RB₄. As another example,transistor cell TC_(3.2), is located in the row between row boundarylines RB₄ and RB₇.

In addition to the preceding, FIG. 7 depicts an alternative embodimentfor transistor cell TC₃, where each instance of such an embodimentincludes a superscript asterisk in the reference identifier—thus, foursuch instances are shown, as TC_(3.4), TC_(3.5), TC_(3.6), and TC_(3.7).For each such alternative embodiment, the spare areas from FIG. 4 areeliminated so that the alternative cell occupies only two rows insteadof three rows as detailed above; however, from FIG. 6 one skilled in theart will now appreciate that if the spare areas of a transistor cell TC₃are removed, then alignment of the modified cell requires that eachboundary end of the cell be aligned along the middle of a row. Toillustrate this aspect, FIG. 7 also illustrates the midpoint of eachrow. By way of examples of this illustration, a row boundary linemidpoint RB_(1.5) is shown midway between row boundary lines BR₁ andRB₂, a row boundary line midpoint RB_(2.5) is shown midway between rowboundary lines BR₂ and RB₃, and so forth for the remaining row boundarylines in FIG. 7. Given these conventions, then note with respect tomodified transistor cell TC_(3.4), it has no spare areas and spans onlytwo rows, where the boundary bottom of that resulting two cell row isaligned with row boundary line midpoint RB_(1.5) and the boundary top ofthat resulting two cell row is aligned with row boundary line midpointRB_(2.5). Similarly, for modified transistor cell TC_(3.5), it also hasno spare areas and spans only two rows, where the boundary bottom ofthat resulting two cell row is aligned with row boundary line midpointRB_(2.5) and the boundary top of that resulting two cell row is alignedwith row boundary line midpoint RB_(3.5). Thus, FIG. 7 illustrates thatif a placement and routing tool is modified so as to be operable tolocate cells on row midpoints, then the preferred embodiment may bemodified so as to eliminate its spare areas and occupy only two rows,albeit aligned between row midpoints. In this instance, such modifiedcells may be aligned in adjacent rows (i.e., in the vertical dimensionin FIG. 7) so that each instance of this alternative preferredembodiment occupies no more area than transistor cell TC₂ of the priorart and with no gaps in that same dimension between adjacent cells. Inthis manner, therefore, the additional performance benefits oftransistor cell TC₃ are realized without any area penalty as compared totransistor cell TC₂.

From the above, it may be appreciated that the preferred embodimentsprovide inventive cell technology, where such technology may beimplemented in data cell libraries and constructed on integratedcircuits. Various benefits have been discussed above, and one skilled inthe art will further appreciate that the preferred embodiments arereadily scalable for use in VLSI applications, thereby improving theentirety of the application. Further, various alternatives have beenprovided according to preferred embodiments, and still others may beascertained by one skilled in the art. Given the preceding, therefore,one skilled in the art should further appreciate that while the presentembodiments have been described in detail, various substitutions,modifications or alterations could be made to the descriptions set forthabove without departing from the inventive scope, as is defined by thefollowing claims.

1. An integrated circuit, comprising: an area having a layout aligned inrows, wherein each row is definable by a pair of row boundaries; aplurality of cells, comprising a first set of cells, wherein each cellin the first set of cells spans at least two rows and comprises: a PMOStransistor having a source/drain region that spans across one of the rowboundaries; and an NMOS transistor having a source/drain region thatspans across one of the row boundaries.
 2. The integrated circuit ofclaim 1 wherein each cell in the first set of cells spans at least threerows.
 3. The integrated circuit of claim 1 wherein each cell in thefirst set of cells spans comprises: a first area extending from a firstrow boundary toward the source/drain region of the PMOS transistor; asecond area extending from a second row boundary toward the source/drainregion of the NMOS transistor; and circuitry located in the first andsecond area.
 4. The integrated circuit of claim 3 wherein the circuitrylocated in the first and second area is selected from a set consistingof an additional transistor that is smaller than the NMOS transistor andthe PMOS transistor, a decoupling capacitor, a diffusion antennaprotection device, and a failure analysis target.
 5. The integratedcircuit of claim 1 wherein the plurality of cells further comprises asecond set of cells, wherein each cell in the second set of cells spansone row.
 6. The integrated circuit of claim 1 wherein the plurality ofcells further comprises a second set of cells, wherein each cell in thesecond set of cells spans two rows.
 7. The integrated circuit of claim 6wherein each cell in the second set of cells comprises: a firsttransistor of a first conductivity type; and a second transistor of asecond conductivity type, wherein a source/drain region of one of thefirst and second transistor comprises two physically separated regions.8. The integrated circuit of claim 6 wherein each cell in the first setof cells spans at least three rows.
 9. The integrated circuit of claim1: wherein the plurality of cells further comprises a second set ofcells, wherein each cell in the second set of cells spans one row; andwherein the plurality of cells further comprises a third set of cells,wherein each cell in the third set of cells spans two rows.
 10. Theintegrated circuit of claim 9 and further comprising a power conductorspanning in a single dimension, parallel to a row in the rows, across acell in the first set, a cell in the second set, and a cell in the thirdset.
 11. A method of operating a computing system to determine data forconstructing an integrated circuit, the method comprising: receivingcircuit node data comprising a description of devices defined byrespective nodes and the functionality of each device as between therespective nodes; for at least some of the devices described in thecircuit node data: selecting a transistor cell from a cell library; andspecifying a location of the selected transistor cell in an area havinga layout aligned in rows, wherein each row is definable by a pair of rowboundaries; wherein the selected transistor cell spans at least two rowsand comprises: a PMOS transistor having a source/drain region that spansacross one of the row boundaries; and an NMOS transistor having asource/drain region that spans across one of the row boundaries.
 12. Themethod of claim 11 wherein the selected transistor cell spans at leastthree rows.
 13. The method of claim 11 wherein the selected transistorcell comprises: a first area extending from a first row boundary towardthe source/drain region of the PMOS transistor; a second area extendingfrom a second row boundary toward the source/drain region of the NMOStransistor; and circuitry located in the first and second area.
 14. Themethod of claim 3 wherein the circuitry located in the first and secondarea is selected from a set consisting of an additional transistor thatis smaller than the NMOS transistor and the PMOS transistor, adecoupling capacitor, a diffusion antenna protection device, and afailure analysis target.
 15. The method of claim 11 wherein the selectedtransistor cell comprises a first selected transistor cell, and furthercomprising selecting a second transistor cell, wherein the secondselected transistor cell cells spans one row.
 16. The method of claim 11wherein the selected transistor cell comprises a first selectedtransistor cell, and further comprising selecting a second transistorcell, wherein the second selected transistor cell cells spans two rows.17. The method of claim 16 wherein the second selected transistor cellcomprises: a first transistor of a first conductivity type; and a secondtransistor of a second conductivity type, wherein a source/drain regionof one of the first and second transistor comprises two physicallyseparated regions.
 18. The method of claim 16 wherein first selectedtransistor cell spans at least three rows.
 19. The method of claim 11wherein the selected transistor cell comprises a first selectedtransistor cell, and further comprising: selecting a second transistorcell, wherein the second selected transistor cell cells spans one row;and selecting a third transistor cell, wherein the third selectedtransistor cell cells spans two rows.
 20. The method of claim 19 andfurther comprising specifying a location of a power conductor spanningin a single dimension, parallel to a row in the rows, across the firstselected transistor cell, the second selected transistor cell, and thethird selected transistor cell.